As modern information technology advances, various types of displays have been widely used in screens for consumer electronic products such as mobile phones, notebook computers, digital cameras, and personal digital assistants (PDAs). Among these displays, liquid crystal displays (LCD) and organic light-emitting diode display (OLED) are the prevailing products in the market due to their advantages of being light-weight, compact, and low in power-consumption. The manufacturing process for both LCD and OLED includes forming semiconductor devices arranged in array on a substrate and the semiconductor devices include thin film transistors (TFTs). TFTs comprise source-/drain-electrodes, a gate electrode, a dielectric layer, a substrate layer, and an active semiconducting layer.
Here and below, active semiconducting layers are to be understood as meaning layers which have charge carrier mobilities of from 1 to 50 cm2/Vs in the case of a component having a channel length of 20 μm at 50 V gate source voltage and 50 V source drain voltage.
Conventionally, thin film transistors include top-gate TFTs and bottom-gate TFTs, depending on whether the gate is positioned on the substrate and below the electrodes or vice versa positioned above the electrodes. These TFTs have one semiconductor layer or stack of layers serving as an active layer.
One problem in the field of metal oxide semiconductor thin film transistors is that during fabrication, e.g., due to high temperature treatment of the semiconductor laminate comprised in the TFT, the surface of the source-/drain-electrode layer is unintentionally oxidized which causes deterioration of the laminate's conduction properties, i.e., by causing parasitic resistance.
It is state of the art to introduce a buffer layer between the source-/drain-electrode layer and the active semiconductor layer, wherein the buffer layer is above the S/D-electrode layers and beneath the active semiconductor layer relative to the substrate layer, in order to reduce S/D-electrode layer oxidation (cf. U.S. Pat. No. 8,338,226, U.S. Pat. No. 8,405,085, US20120211746, US20120248446, US20130037797, and US20130056726). U.S. Pat. No. 8,247,276 teaches to introduce a buffer layer between the source-/drain-electrode layer and the active semiconductor layer, wherein the buffer layer is beneath the S/D-electrode layers and above the active semiconductor layer relative to the substrate layer.
However, the resulting semiconductor laminates are still prone to influences on the S/D-electrode layer and thus do not have the desired conductive properties.
It was therefore an object of the present invention to provide a semiconductor laminate which overcomes the above limitations and has improved conductive properties.
The inventors of the present invention found out that due to the procedural steps in laminate alignment, e.g., during a high temperature treatment during the provision of the active oxide semiconductor layer, the buffer layer covered source-/drain-electrode layer is only vertically protected but not protected against horizontal influences which are sufficient to significantly disturb the contact between the side surface of the source-/drain-electrode layer and the active oxide semiconductor layer.
Accordingly, even though the above buffer layer is implemented as a measure to improve protection of the source-/drain-electrode layer, oxidation of this layer occurs at the side surface where it contacts the active oxide semiconductor layer. Thus, the laminate manufacturing process still negatively influences the total conductivity of the laminate by raising the contact resistance. In agreement with this finding, the inventors found that this effect contributes to a reduced on-current of the laminate.
Furthermore, the inventors surprisingly discovered that the above problem is solved by the provision of a carrier injection layer at the bottom of the source-/drain-electrode layer, wherein the active oxide semiconductor layer is in direct contact with the gate insulator layer, the injection layer, and the source-/drain-electrode. Specifically advantageous is, if the active oxide semiconductor is provided on a source-/drain-electrode layer which is deposited on a carrier injection layer and wherein the active oxide semiconductor layer is in direct contact with the gate insulator layer, the injection layer, and the source-/drain-electrode.
The problem may also be solved by the provision of a carrier injection layer at the bottom of the source-/drain-electrode layer, wherein the injection layer is in direct contact with the source-/drain-electrode and the active oxide semiconductor layer is in direct contact with the injection layer via a side surface of the injection layer and in direct contact with the S/D electrode layer via a side surface of the S/D electrode layer.
The injection layer is capable of injecting electrons into the active oxide semiconductor layers.
The TFT laminates have a significantly reduced contact resistance between the source-/drain-electrode layer and the semiconductor layer, leading to an increase in on-current and electron mobility.
In addition, the inventors found that it is further beneficial to combine the above injection layer with a protection layer arranged on the top of the source-/drain-electrode layer to prevent the above mentioned vertical electrode surface oxidation during the laminate annealing process. Thus, the combination of injection and protection layers further improves the conductivity of the laminate and the resulting TFT devices.